There’s this video going around “An Open Source CPU!?” about SiFive’s implementation of RISC-V being “an open source CPU”, but it’s so duplicitous that I wanted to tear out my hair as I watched it. RISC-V is an interesting and worthy project, but the video is misleading in so many ways it’s hard to know where to begin.
For one thing, the x86-16 ISA wasn’t just hacked up in a few weeks from nothing. Intel’s architects spent months on it, and it was based on Intel’s 8-bit 8080 ISA, which was in turn informed by the experience of their earlier 8008 ISA. It had also already been on the market for a few years by the time IBM got around to the PC. For another thing, the x86-32 ISA was hardly lacking competition during its era of desktop dominance, with Motorola’s 68000, IBM’s Power Architecture, and DEC’s Alpha all big-name-backed ISAs trying to displace it. When the time came for 64-bit PCs, even Intel itself failed in its attempt to push a new kind of ISA for the PC market with its Itanium architecture.
Regarding the RISC/CISC divide, it is true that CISC processors don’t execute their ISA instructions directly in hardware now, but instead run RISC microcode (because RISC instruction-handling circuitry executes faster and is easier to design) for a CISC ISA interpreter. But that doesn’t mean RISC is best for application or system code, because microcode has no instruction cache! In the embedded systems and mobile-device markets, ARM had to abandon the “elegant” simplicity of their RISC ISA and supplement it with non-RISC “Thumb” and then “Thumb-2” extensions to raise its code density (important on small processors with small instruction caches) to keep x86 ISA microcontrollers, with their dense CISC code and ever-decreasing prices, at bay. As is often the case when competing technologies butt heads, the best solution is to find a way to use the advantages of both!
The video’s title is “An Open Source CPU!?” — and this is its biggest lie, because SiFive’s CPU being open is presented as something new, which is very much not true. Even if you dismiss all CISC designs as unworthy, there are open RISC specs with open source implementations that predate RISC-V, both grassroots and of commercial origin. Furthermore, SiFive’s CPU not only isn’t the first open source RISC processor, it’s not even the first open source RISC-V processor! You can get open source implementations of RISC-V here (VexRiscv) or here (ORCA) or here (Sodor).
This video is just an advertisement of SiFive’s pretending to be an independent informational video, spreading misinformation about the history and present state of microprocessors. (For your amusement, go and pause the video around 6m12s — the presenter is stating the inferiority of other open ISAs compared to RISC-V while showing a changelog on GitHub. But the changelog shown is not that of anything to do with another ISA, but the opposite: it’s actually the changelog for the port of gdb to RISC-V! The presenter could have grabbed a screenshot from the GitHub pages of the ZPU project with insignificant additional effort and shown something that was actually applicable to his claim, but once you’ve stepped off the straight-and-narrow path of honesty onto the wide highway of dishonesty, why bother?)
In short, that video is complete and utter BS, the presenter should be downvoted into YouTube oblivion, you should never pay one red cent for anything from SiFive, and RISC-V deserves better. It’s strong enough that it should be able to fight honestly, and having its proponents descend to dishonest shilling for one corporation is disgraceful.
